Abstract: This paper presents a 6-bit 3.4 GS/s flash ADC in 65 nm CMOS. The proposed 4× time-domain interpolation technique allows the reduction of the number of comparators from the conventional 63 ...
Abstract: We developed a compact model for program transient simulation of 3-D charge-trap NAND flash on a bitline (BL) string level. By implanting the trapped charge parameters and the solutions ...
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