IEEE

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference

Abstract: This work presents a 6.5-to-8-GHz cascaded dual-fractional-N digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with ...
IEEE

Reference current extraction for three-phase four-wire h-bridge DSTATCOM using SOGI-PLL algorithm

Abstract: In this paper, a new Second Order Generalized Integrator - Phase Locked Loop control algorithm for reactive power compensation, load balancing, harmonic elimination and neutral current ...